1. Field of the Invention
This invention generally relates to CMOS fabrication processes and, more particularly, to a CMOS device that uses a stacked metal structure, with a metal barrier to protect a metal gate electrode, that does not affect the gate electrode work function.
2. Description of the Related Art
The threshold voltages (Vth) of the NMOS and PMOS components in a complementary metal oxide semiconductor (CMOS) circuit largely dictate the speed, standby current, and operating current performance characteristics. The Vth must be set to maximize the “on” current, while minimizing the “off” current. Usually this is a trade off that is determined by the circuit design and application. Typically, the Vth is adjusted through fine-tuning of the doping level in the channel region of the transistors with a Vth adjust implant. As the feature size of transistors continues to scale down, the struggle to minimize short channel effects, and reduce punchthrough and drain-induced barrier lowering with implantations and anneals, ultimately limit the device speed.
As an alternative method of adjusting Vth, the work function of the gate can be controlled. This is usually done with implants into the gate polysilicon, where donor type dopant is placed in the gate for NMOS, and acceptor dopants into PMOS gates. The use of doped polysilicon gates presents a different set of problems, however. Dopant diffusion, through the gate dielectric into the channel, affects the Vth polysilicon depletion near the gate dielectric, and limits the performance of the transistors.
Doped polysilicon has been the gate material of choice for the last several generations of microelectronics technology. To achieve low Vth devices (required for high performance), p+ poly is used for PMOS and n+ poly is used for NMOS. As devices are scaled, the thickness of the poly-Si gate is decreased. In order to maintain low sheet resistance and a large effective oxide capacitance (i.e. minimize poly depletion effects) it has been necessary to increase the poly doping density with each successive generation. This has led to the problem of channel autodoping in which boron (B) from the gate poly diffuses across the thin gate dielectric and into the channel, causing Vth variations that degrade device performance.
This diffusion, or autodoping problem is addressed with the use of metal gate materials. With metal gate technologies, the choice of an appropriate work function material is necessary for the N and P MOSFETs. The work function is the energy required to remove an electron from the Fermi level to vacuum. The work function of different materials, and different metals, varies. Since the NMOS and PMOS work function requirements are different, the metal materials are typically different. Thus, dual metals, with work functions corresponding to p+ and n+ poly Si) will be required for CMOS circuits.
However, the use of completely different metal materials for NMOS and PMOS gates results in additional fabrication steps and undesired complexity.
It has been shown that many of the desirable gate metal materials have adhesion and/or stability problems when placed in direct contact with the SiO2 or high k gate dielectrics, such as HfO2 or ZrO2. For example, it is known that Pt does not adhere well to SiO2, and metals such as Ti, Hf, or Zr, scavenge O, reducing the underlying dielectric film, causing degradation and increased leakage.
It would be advantageous if the above-mention diffusion and adhesion problems could be addressed using a gate electrode diffusion barrier.
It would be advantageous if a gate electrode diffusion barrier could be used that didn't contribute to the work function of a metal gate electrode.
It would be advantageous if a gate electrode diffusion barrier were conductive, so that it did not contribute to the capacitance of the gate stack.